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[/] [amber/] [trunk/] [hw/] [tools/] - Rev 63

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Last modification

  • Rev 63 2013-04-28 10:55:21 GMT
  • Author: csantifort
  • Log message:
    Add support for Xilinx ISim Verilog simulator.
    Remove Virtex-6 files.
Path Last modification Log RSS feed
[FOLDER] amber/ 63  4228d 04h csantifort View Log RSS feed
[NODE][FOLDER] branches/ 1  5085d 00h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5085d 00h root View Log RSS feed
[NODE][FOLDER] trunk/ 63  4228d 04h csantifort View Log RSS feed
[NODE][NODE][FOLDER] doc/ 48  4880d 00h csantifort View Log RSS feed
[NODE][NODE][FOLDER] hw/ 63  4228d 04h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] fpga/ 63  4228d 04h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] isim/ 63  4228d 04h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 61  4514d 23h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tests/ 60  4732d 19h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tools/ 63  4228d 04h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] all.sh 63  4228d 04h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] get_timeout.sh 56  4802d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] run.sh 61  4514d 23h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] set_timeout.sh 56  4802d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] vlog/ 63  4228d 04h csantifort View Log RSS feed
[NODE][NODE][FOLDER] sw/ 62  4380d 17h csantifort View Log RSS feed

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