OpenCores
URL https://opencores.org/ocsvn/amber/amber/trunk

Subversion Repositories amber

[/] [amber/] [trunk/] [hw/] [vlog/] [system/] - Rev 13

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 13 2011-02-17 15:09:27 GMT
  • Author: csantifort
  • Log message:
    Bug fix - added an extra state to the rx state machine to properly align
    reading the uart input to the middle of each bit.
Path Last modification Log RSS feed
[FOLDER] amber/ 13  4875d 01h csantifort View Log RSS feed
[NODE][FOLDER] branches/ 1  4931d 02h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4931d 02h root View Log RSS feed
[NODE][FOLDER] trunk/ 13  4875d 01h csantifort View Log RSS feed
[NODE][NODE][FOLDER] doc/ 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][FOLDER] hw/ 13  4875d 01h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] fpga/ 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tests/ 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tools/ 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] vlog/ 13  4875d 01h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] amber/ 9  4891d 05h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ethmac/ 2  4904d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] lib/ 12  4875d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] system/ 13  4875d 01h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] afifo.v 2  4904d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] boot_mem.v 2  4904d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] clocks_resets.v 2  4904d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] ddr3_afifo.v 2  4904d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] interrupt_controller.v 2  4904d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] main_mem.v 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] memory_configuration.v 10  4891d 05h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_addresses.v 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] system.v 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] system_config_defines.v 10  4891d 05h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] test_module.v 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] timer_module.v 2  4904d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] uart.v 13  4875d 01h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] wb_ddr3_bridge.v 2  4904d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] wb_xs6_ddr3_bridge.v 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] wb_xv6_ddr3_bridge.v 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] wishbone_arbiter.v 2  4904d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] tb/ 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] xs6_ddr3/ 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] xv6_ddr3/ 11  4890d 02h csantifort View Log RSS feed
[NODE][NODE][FOLDER] sw/ 11  4890d 02h csantifort View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.