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[/] [amber/] [trunk/] [hw/] [vlog/] [system/] - Rev 14

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Last modification

  • Rev 14 2011-02-17 15:11:11 GMT
  • Author: csantifort
  • Log message:
    Re-wrote the behavioral clock generation code to more accurately
    calculate the sys_clk frequency. The previous version was not
    producing the correct frequency at higher frequenies due to
    rounding errors.
Path Last modification Log RSS feed
[FOLDER] amber/ 14  5032d 20h csantifort View Log RSS feed
[NODE][FOLDER] branches/ 1  5088d 21h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5088d 21h root View Log RSS feed
[NODE][FOLDER] trunk/ 14  5032d 20h csantifort View Log RSS feed
[NODE][NODE][FOLDER] doc/ 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][FOLDER] hw/ 14  5032d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] fpga/ 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tests/ 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] tools/ 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][FOLDER] vlog/ 14  5032d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] amber/ 9  5049d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ethmac/ 2  5061d 18h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] lib/ 12  5032d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] system/ 14  5032d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] afifo.v 2  5061d 18h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] boot_mem.v 2  5061d 18h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] clocks_resets.v 14  5032d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] ddr3_afifo.v 2  5061d 18h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] interrupt_controller.v 2  5061d 18h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] main_mem.v 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] memory_configuration.v 10  5049d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] register_addresses.v 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] system.v 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] system_config_defines.v 10  5049d 00h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] test_module.v 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] timer_module.v 2  5061d 18h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] uart.v 13  5032d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] wb_ddr3_bridge.v 2  5061d 18h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] wb_xs6_ddr3_bridge.v 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] wb_xv6_ddr3_bridge.v 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] wishbone_arbiter.v 2  5061d 18h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] tb/ 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] xs6_ddr3/ 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] xv6_ddr3/ 11  5047d 20h csantifort View Log RSS feed
[NODE][NODE][FOLDER] sw/ 11  5047d 20h csantifort View Log RSS feed

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