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[/] [axi_vga/] [trunk/] [rtl/] - Rev 4

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  • Rev 4 2019-11-20 07:48:27 GMT
  • Author: hugoliu
  • Log message:
    The source code in the rtl direction. I add the model files and sim file. I use the modelsim to simulate it. I use the AXI master port to access the DRAM and send image data to TFT.
Path Last modification Log RSS feed
[FOLDER] axi_vga/ 4  1815d 19h hugoliu View Log RSS feed
[NODE][FOLDER] branches/ 1  1815d 20h root View Log RSS feed
[NODE][FOLDER] tags/ 1  1815d 20h root View Log RSS feed
[NODE][FOLDER] trunk/ 4  1815d 19h hugoliu View Log RSS feed
[NODE][NODE][FOLDER] model/ 3  1815d 19h hugoliu View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 4  1815d 19h hugoliu View Log RSS feed
[NODE][NODE][NODE][FILE] vga_out.v 4  1815d 19h hugoliu View Log RSS feed
[NODE][NODE][FOLDER] sim/ 2  1815d 19h hugoliu View Log RSS feed

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