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[/] [copyblaze/] [trunk/] [copyblaze/] [rtl/] [vhdl/] [ip/] [wb_3p_spram_wrapper/] - Rev 65
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Last modification
- Rev 65 2011-12-15 21:55:10 GMT
- Author: ameziti
- Log message:
- DEV:
- design an Sram Wishbone memory with WAIT STATES.