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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] - Rev 14

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Last modification

  • Rev 14 2009-01-09 20:45:15 GMT
  • Author: fpga_is_funny
  • Log message:
    More optimizations...
    - Second Phaze of removing unused nets & registers
    - Added Verilog source on demand by some customers (for trial use)
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[FOLDER] branches/ 8  5789d 09h fpga_is_funny View Log RSS feed
[FOLDER] tags/ 10  5789d 09h View Log RSS feed
[FOLDER] trunk/ 14  5784d 10h fpga_is_funny View Log RSS feed

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