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[/] [dblclockfft/] [trunk/] [bench/] [cpp/] - Rev 13

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Last modification

  • Rev 13 2015-03-06 20:47:14 GMT
  • Author: dgisselq
  • Log message:
    I updated the butterfly testbench to automatically determine the delay
    internal to the chip and multiply, and then to use that delay in determining
    whether the values were accurate or not. This is better than the fixed
    delay approach that was used before. The change was necessitated by an
    attempt to use a different multiply structure that had a different
    internal delay to it. (The multiply didn't work out, as it only worked
    on operands with identical numbers of bits.)
Path Last modification Log RSS feed
[FOLDER] dblclockfft/ 13  3550d 19h dgisselq View Log RSS feed
[NODE][FOLDER] branches/ 1  3562d 20h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3562d 20h root View Log RSS feed
[NODE][FOLDER] trunk/ 13  3550d 19h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 13  3550d 19h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] cpp/ 13  3550d 19h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] butterfly_tb.cpp 13  3550d 19h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] dblrev_tb.cpp 6  3557d 13h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] dblstage_tb.cpp 6  3557d 13h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] fftstage_o2048_tb.cpp 9  3556d 19h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] fft_tb.cpp 9  3556d 19h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] Makefile 9  3556d 19h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] mpy_tb.cpp 6  3557d 13h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] qtrstage_tb.cpp 6  3557d 13h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 12  3554d 01h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 9  3556d 19h dgisselq View Log RSS feed

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