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[/] [dblclockfft/] [trunk/] [doc/] [src/] - Rev 25

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  • Rev 25 2015-04-13 14:08:19 GMT
  • Author: dgisselq
  • Log message:
    The documentation has been changed to bring it closer to the example
    specification document. The big change is that the first line, the
    headline if you will, of each table has een adjusted to have a gray
    background.

    The second and bigger change is in the fftgen software itself, or more
    specifically to the code that it produces. I had the opportunity to build
    the code using Xilinx's ISE and spent some time getting rid of warnings
    during the build. As a result, registers that need initial conditions
    now have initial conditions. In a similar manner I have trimmed out
    registers that were unused. The resulting code continues to pass all
    test benches, although I will admit that the automated testing of the
    whole fft or ifft via there test benches, fft_tb and ifft_tb, continues
    to be a less than automated process than it should be. Therefore, these
    test benches always "pass" and only a manual examination of the results
    can be used to confirm their success.
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[NODE][FOLDER] branches/ 1  3569d 10h root View Log RSS feed
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[NODE][FOLDER] trunk/ 25  3519d 16h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] bench/ 23  3549d 06h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] doc/ 25  3519d 16h dgisselq View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 25  3519d 16h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] gpl-3.0.tex 3  3564d 15h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] gqtekspec.cls 25  3519d 16h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] GT.eps 10  3561d 03h dgisselq View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] spec.tex 22  3550d 08h dgisselq View Log RSS feed
[NODE][NODE][FOLDER] sw/ 25  3519d 16h dgisselq View Log RSS feed

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