Subversion Repositories dblclockfft

Last modification

• Rev 26 2015-06-02 14:36:44 GMT
• Author: dgisselq

• Log message:

  A lot of updates and upgrades in this release. Specifically, work took place
  over the last several days to demonstrate this FFT on an FPGA. It was
  demonstrated on the Xilinx Artix-7 found on a Basys-3 development board.
  Part of the effort stemmed around making certain that the DSPs were used
  optimally, part of it stemmed around making certain that various parts of the
  FFT could use block RAM-type memories. The other massive change involved
  removing as much unnecessary logic as possible, so that two 16-bit 1k FFTs
  could fit onto this part--together with other glue logic. The bottom line,
  though, is that it all now works. Specifically, I've tested it successfully
  with
  
  fftgen -f <FFTSIZE> -n 16 -m 16 -p 7 -c 1 -x 1
  
  and with FFTSIZEs of 32, 64, 128, 256, 512, and 1024.
  
  Oh, I should mention that there's also an undocumented DEBUG interface to the
  part, and I fixed where the Verilog files went when given an argument, so
  that they actually went to the directory specified. Minor updates have taken
  place to the documentation format, making it match the documentation format
  for other opencores projects that I've produced.
  
  On a sadder note, the Verilator simulation fft_tb no longer works. (Yeah, get
  that---the FFT implementation works but Verilator does not. Sigh).