Subversion Repositories dblclockfft

Last modification

• Rev 29 2015-07-04 15:12:23 GMT
• Author: dgisselq

• Log message:

  Checking in a lot of changes here. These changes were focused on two
  things primarily: 1st the ability to match, in bench testing, the bench
  test to the configuration of the generated FFT. For this purpose, the
  fftgen program now creates fftsize.h and ifftsize.h header files. These
  header files contain the parameters that were used in the creation of the
  various verilog files, and therefore the C++ test benches may now be compiled
  to match the test files. The 2nd change is the multiply. Based upon a
  set of slides from Xilinx, I rebuilt my shiftaddmpy into a longbimpy.
  (Think if 'bimpy' as a 'bi', or two-bit, 'mpy', or multiply.) Longbimpy
  depends upon bimpy, an optimized 2xN bit multiply--optimized for 6-bit
  LUTs with carry chains. Longbimpy simply expands that capability to a
  NxN bit multiply. Sadly, the longbimpy approach increased my area on the
  chip when it was supposed to be a cheaper multiply, so I may well take it
  back out in the future.