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Subversion Repositories ddr2_sdram

[/] [ddr2_sdram/] [trunk/] [Testbench_DDR2/] [Clock/] - Rev 4

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Last modification

  • Rev 4 2012-06-03 16:51:21 GMT
  • Author: john_fpga
  • Log message:
    add : Testbenches (Clock,Read,Write)
Path Last modification Log RSS feed
[FOLDER] ddr2_sdram/ 4  4551d 10h john_fpga View Log RSS feed
[NODE][FOLDER] branches/ 1  4839d 16h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4839d 16h root View Log RSS feed
[NODE][FOLDER] trunk/ 4  4551d 10h john_fpga View Log RSS feed
[NODE][NODE][FOLDER] ipcore_dir/ 2  4839d 16h john_fpga View Log RSS feed
[NODE][NODE][FOLDER] iseconfig/ 2  4839d 16h john_fpga View Log RSS feed
[NODE][NODE][FOLDER] MIG_Settings/ 3  4839d 15h john_fpga View Log RSS feed
[NODE][NODE][FOLDER] Prj12_Impact_xdb/ 2  4839d 16h john_fpga View Log RSS feed
[NODE][NODE][FOLDER] Testbench_DDR2/ 4  4551d 10h john_fpga View Log RSS feed
[NODE][NODE][NODE][FOLDER] Clock/ 4  4551d 10h john_fpga View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] Clock_01_Timing.JPG 4  4551d 10h john_fpga View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] Clock_02_Reset.JPG 4  4551d 10h john_fpga View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] Clock_03_Period.JPG 4  4551d 10h john_fpga View Log RSS feed
[NODE][NODE][NODE][NODE][DB-FILE] Clock_04_Phase_Shift.JPG 4  4551d 10h john_fpga View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] Testbench_DDR2_Core.vhd 4  4551d 10h john_fpga View Log RSS feed
[NODE][NODE][NODE][FOLDER] Read/ 4  4551d 10h john_fpga View Log RSS feed
[NODE][NODE][NODE][FOLDER] Write/ 4  4551d 10h john_fpga View Log RSS feed
[NODE][NODE][FOLDER] _xmsgs/ 2  4839d 16h john_fpga View Log RSS feed

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