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[/] [edge/] [trunk/] [HW/] [Boards/] [Atlys/] - Rev 2

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  • Rev 2 2014-03-02 19:24:42 GMT
  • Author: heshamelmatary
  • Log message:
    Initiate project repository
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[FOLDER] edge/ 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][FOLDER] branches/ 1  3924d 03h root View Log RSS feed
[NODE][FOLDER] tags/ 1  3924d 03h root View Log RSS feed
[NODE][FOLDER] trunk/ 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][FOLDER] DOC/ 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][FOLDER] HW/ 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][NODE][FOLDER] Boards/ 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] Atlys/ 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] EdgeMemMap.bmm 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] edge_atlys.bit 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] edge_atlys_constraints.ucf 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] edge_atlys_processor.v 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] instruction_memory.v 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] memory_system.v 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] UART_TX_CTRL.vhd 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][NODE][FOLDER] Verilog/ 2  3924d 02h heshamelmatary View Log RSS feed
[NODE][NODE][FOLDER] SW/ 2  3924d 02h heshamelmatary View Log RSS feed

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