OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] - Rev 15

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 15 2001-08-06 14:44:29 GMT
  • Author: mohor
  • Log message:
    A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
    Include files fixed to contain no path.
    File names and module names changed ta have a eth_ prologue in the name.
    File eth_timescale.v is used to define timescale
    All pin names on the top module are changed to contain _I, _O or _OE at the end.
    Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
    and Mdo_OE. The bidirectional signal must be created on the top level. This
    is done due to the ASIC tools.
Path Last modification Log RSS feed
[FOLDER] branches/ 1  8629d 17h View Log RSS feed
[FOLDER] tags/ 3  8629d 17h View Log RSS feed
[FOLDER] trunk/ 15  8492d 00h mohor View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.