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[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 22
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Last modification
- Rev 22 2001-10-19 08:46:53 GMT
- Author: mohor
- Log message:
- eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.