Subversion Repositories gecko3

Last modification

• Rev 18 2010-01-15 10:36:10 GMT
• Author: nussgipfel

• Log message:

  I achieved now stable OUT transfers (from the PC to the FPGA) with working throtling (when the FPGA consumes data slower than the host delivers).
  The basics needed for this are implemented in the FPGA like handshaking with the FX2 and clock domain transistion from the Interface clock to the user defined system clock.
  
  in the gpif_com_test.vhd is a message rom, containing a prepared answer message to generate an IN transfer. this is needed for the next step.