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Subversion Repositories genesys_ddr2

[/] [genesys_ddr2/] [trunk/] [bench/] - Rev 2

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Last modification

  • Rev 2 2013-05-06 14:26:49 GMT
  • Author: oana.boncalo
  • Log message:
    Oana Boncalo - First upload of DDR2 mem controller
Path Last modification Log RSS feed
[FOLDER] genesys_ddr2/ 2  4086d 02h oana.boncalo View Log RSS feed
[NODE][FOLDER] branches/ 1  4089d 01h root View Log RSS feed
[NODE][FOLDER] tags/ 1  4089d 01h root View Log RSS feed
[NODE][FOLDER] trunk/ 2  4086d 02h oana.boncalo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 2  4086d 02h oana.boncalo View Log RSS feed
[NODE][NODE][NODE][FOLDER] Xilinx_MIG_bench/ 2  4086d 02h oana.boncalo View Log RSS feed
[NODE][NODE][NODE][FILE] test_DDR2_wb.v 2  4086d 02h oana.boncalo View Log RSS feed
[NODE][NODE][NODE][FILE] wishbone_mock.v 2  4086d 02h oana.boncalo View Log RSS feed
[NODE][NODE][FOLDER] par/ 2  4086d 02h oana.boncalo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 2  4086d 02h oana.boncalo View Log RSS feed

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