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[/] [ima_adpcm_enc_dec/] [trunk/] [verilog/] [rtl/] - Rev 3
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Last modification
- Rev 3 2011-09-23 21:17:50 GMT
- Author: motilito
- Log message:
- Added Altera FPGA synthesis results to the specifications document.
Changed an assignment statement in the encoder module to clear a synthesis warning.