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[/] [minsoc/] [branches/] [rc-1.0/] [bench/] [verilog/] - Rev 133
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Last modification
- Rev 133 2011-11-07 09:48:11 GMT
- Author: rfajardo
- Log message:
- Roll back minsoc_bench.v to timed simulation. Merge minsoc_bench_core and minsoc_bench_clock again.
Applying Rubén Diez patch to avoid warnings on firmware load for simulation.