Subversion Repositories minsoc

Last modification

• Rev 6 2009-09-28 09:37:18 GMT
• Author: rfajardo

• Log message:

  No implementation relevant changes.
  
  Testbench used generic memory from minsoc_onchip_ram.v has been changed to reflect the correct model of the FPGA's onchip rams: address register and write accesses are sensitive to rising clock edge.
  
  Documentation updated to reflect another trial and next steps to speed up the memory access from 2 clocks to 1. The negated clock approach is not standard. The right way to do it would be to use the wishbone signals cti and bte and change the minsoc_onchip_ram_top.v.