URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [branches/] [rc-1.0/] [prj/] [src/] - Rev 131

Rev 131 2011-11-03 13:58:53 GMT
Author: rfajardo
Log message:
Renaming testbench modules. Adding to ifdefs without which the testbench generation can fail.

Path	Last modification			Log	RSS feed
minsoc/	131	4751d 06h	rfajardo	View Log	RSS feed
branches/	131	4751d 06h	rfajardo	View Log	RSS feed
rc-1.0/	131	4751d 06h	rfajardo	View Log	RSS feed
backend/	124	4752d 05h	rfajardo	View Log	RSS feed
bench/	131	4751d 06h	rfajardo	View Log	RSS feed
doc/	101	4794d 13h	rfajardo	View Log	RSS feed
prj/	131	4751d 06h	rfajardo	View Log	RSS feed
altera/	97	4803d 11h	rfajardo	View Log	RSS feed
scripts/	110	4758d 22h	rfajardo	View Log	RSS feed
sim/	97	4803d 11h	rfajardo	View Log	RSS feed
src/	131	4751d 06h	rfajardo	View Log	RSS feed
blackboxes/	113	4758d 06h	rfajardo	View Log	RSS feed
adbg_top.prj	85	4809d 04h	rfajardo	View Log	RSS feed
altera_virtual_jtag.prj	96	4803d 22h	javieralso	View Log	RSS feed
ethmac.prj	120	4758d 03h	rfajardo	View Log	RSS feed
jtag_top.prj	85	4809d 04h	rfajardo	View Log	RSS feed
minsoc_bench.prj	131	4751d 06h	rfajardo	View Log	RSS feed
minsoc_top.prj	89	4809d 03h	rfajardo	View Log	RSS feed
or1200_top.prj	110	4758d 22h	rfajardo	View Log	RSS feed
uart_top.prj	85	4809d 04h	rfajardo	View Log	RSS feed
xilinx/	97	4803d 11h	rfajardo	View Log	RSS feed
rtl/	110	4758d 22h	rfajardo	View Log	RSS feed
sim/	121	4758d 00h	rfajardo	View Log	RSS feed
sw/	80	4827d 09h	rfajardo	View Log	RSS feed
syn/	121	4758d 00h	rfajardo	View Log	RSS feed
utils/	122	4757d 23h	rfajardo	View Log	RSS feed
tags/	42	4984d 06h	rfajardo	View Log	RSS feed
trunk/	108	4759d 03h	rfajardo	View Log	RSS feed