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[/] [minsoc/] [branches/] [verilator/] - Rev 129
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Last modification
- Rev 129 2011-11-03 00:31:18 GMT
- Author: rfajardo
- Log message:
- Removing bugs introduced when splitting clocks and reset.
1) NEGATIVE_RESET or POSITIVE_RESET were missing as definition on minsoc_bench_clock.v (include minsoc_defines.v).
2) wait for reset on minsoc_bench.v to assert design_ready