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[/] [minsoc/] [branches/] [verilator/] [backend/] - Rev 99
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Last modification
- Rev 99 2011-09-12 09:30:45 GMT
- Author: rfajardo
- Log message:
- backend/altera_3c25_board/minsoc_defines.v: if GENERIC_FPGA selected, undefine ALTERA_FPGA and FPGA_FAMILY to avoid vendor specific code to flow into the simulation. If you don't do it, generate_bench fails.