Subversion Repositories minsoc

Last modification

• Rev 70 2011-05-10 10:06:07 GMT
• Author: rfajardo

• Log message:

  Including a global timescale under minsoc/rtl/verilog to control simulation. It is under the implementation because the implementation files include it.
  
  Removing timescale definition of minsoc_bench_defines.v files.
  
  Creating a modelsim simulation directory. Everything is working under Linux. For Windows, run_sim.sh has to be changed:
  -pli ../../bench/verilog/vpi/jp-io-vpi.so
  to:
  -pli ../../bench/verilog/vpi/jp-io-vpi.dll
  
  These files have to be compiled/copied from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_platform to minsoc/bench/verilog/vpi.