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[/] [minsoc/] [branches/] [verilator/] [bench/] [verilog/] [sim_lib/] - Rev 17
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Last modification
- Rev 17 2009-11-17 14:38:49 GMT
- Author: rfajardo
- Log message:
- Ethernet testbench speed penalty solved. Now Ethernet of testbench and minsoc can be enabled by only uncommenting `define ETHERNET on minsoc_defines.v.
send_mac, get_mac and uart_send tasks have been included/improved. Also a testbench, which works for both included firmwares is added. (eth and uart)
If ETHERNET is defined for the SoC, both firmwares will complete successfully. If not, the eth firmware will stall when trying to access the Ethernet module.