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https://opencores.org/ocsvn/minsoc/minsoc/trunk
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[/] [minsoc/] [branches/] [verilator/] [sim/] [run/] - Rev 34
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Last modification
- Rev 34 2010-10-15 14:35:25 GMT
- Author: rfajardo
- Log message:
- start_server changed: '-t' option of adv_jtag_bridge for vpi connection on simulation removed. or1200_v3 will not pass on CPU self test.
FAQ completed with asked questions since Februrary 2010.
INSTALL informs bsdl files only have to be copied to home directory for Xilinx devices.
synthesis_examples title includes Minimal OpenRISC System on Chip.