OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [bench/] [verilog/] - Rev 11

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 11 2009-10-23 14:49:17 GMT
  • Author: rfajardo
  • Log message:
    External interrupt processing was being run multiple times because:
    -external level interrupts have to be cleared
    -internal interrupt status register has to be cleared
    Since internal interrupt status register was being cleared before external level interrupts clearance, these internal interrupt status was being overwritten inbetween.

    Solution:
    -move status register reset to end of interrupt handler instead of beginning.

    Testbench signal uart_srx initialized now.
Path Last modification Log RSS feed
[FOLDER] minsoc/ 11  5515d 09h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  5550d 14h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5550d 14h root View Log RSS feed
[NODE][FOLDER] trunk/ 11  5515d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 2  5550d 12h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 11  5515d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] verilog/ 11  5515d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim_lib/ 10  5529d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] vpi/ 4  5546d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] eth_phy.v 2  5550d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] eth_phy_defines.v 2  5550d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_bench.v 11  5515d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_bench_defines.v 7  5536d 08h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_memory_model.v 2  5550d 12h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] tb_eth_defines.v 2  5550d 12h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 6  5540d 15h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 7  5536d 08h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 10  5529d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 11  5515d 09h rfajardo View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.