OpenCores
URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [prj/] - Rev 108

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 108 2011-10-26 16:48:51 GMT
  • Author: rfajardo
  • Log message:
    Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

    Icarus Verilog and Altera synthesis are working as well. Job done!
Path Last modification Log RSS feed
[FOLDER] minsoc/ 108  4778d 13h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  5546d 20h root View Log RSS feed
[NODE][FOLDER] tags/ 42  5003d 16h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  4778d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 105  4778d 21h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  4947d 20h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  4813d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 108  4778d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  4822d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 108  4778d 13h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  4822d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 96  4823d 08h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  4822d 21h rfajardo View Log RSS feed
[NODE][NODE][NODE][FILE] Makefile 104  4785d 20h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  4828d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 104  4785d 20h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 80  4846d 19h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 107  4778d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 106  4778d 19h rfajardo View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.