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[/] [minsoc/] [trunk/] [prj/] [altera/] - Rev 175

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  • Rev 97 2011-09-12 08:54:47 GMT
  • Author: rfajardo
  • Log message:
    As proposed by Javier Almansa automatically generated project files for simulation and synthesis are out of revision control. Instead, the backend configure scripts run the prj/Makefile now to generate the project files prior to configuration of SoC for a specific board.
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[FOLDER] minsoc/ 175  4364d 10h rfajardo View Log RSS feed
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[NODE][NODE][FOLDER] backend/ 174  4399d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 162  4842d 13h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  4963d 21h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 158  4857d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  4972d 19h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 141  4901d 18h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  4972d 19h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 158  4857d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  4972d 19h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 175  4364d 10h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 166  4748d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 158  4857d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 141  4901d 18h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 170  4516d 13h ConX. View Log RSS feed

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