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[/] [minsoc/] [trunk/] [prj/] [scripts/] - Rev 108

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Last modification

  • Rev 108 2011-10-26 16:48:51 GMT
  • Author: rfajardo
  • Log message:
    Scripts updates to correct paths when working under Windows. Now, ModelSim, Xilinx and Altera synthesis are working on Windows through batch files.

    Icarus Verilog and Altera synthesis are working as well. Job done!
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[FOLDER] minsoc/ 108  5056d 17h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 1  5825d 00h root View Log RSS feed
[NODE][FOLDER] tags/ 42  5281d 19h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 108  5056d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 105  5057d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 71  5225d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  5092d 02h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 108  5056d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  5101d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 108  5056d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] altprj.sh 107  5056d 20h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] simverilog.sh 108  5056d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] simvhdl.sh 108  5056d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xilinxprj.sh 108  5056d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] xilinxxst.sh 108  5056d 17h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  5101d 01h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 96  5101d 12h javieralso View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  5101d 01h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 88  5106d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 104  5063d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 80  5124d 23h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 107  5056d 20h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 106  5056d 23h rfajardo View Log RSS feed

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