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[/] [minsoc/] [trunk/] [prj/] [src/] - Rev 175

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  • Rev 158 2012-01-05 19:32:03 GMT
  • Author: rfajardo
  • Log message:
    Adding de2_115_board port, thanks to Richard Hasha.

    Support to JSP (JTAG Serial Port) working well. Also provided by Richard Hasha.

    Different interconnect configurations per board are not straightforward on MinSoC. New added modules or definitions for addresses have to be carried over to other boards. Furthermore, extra modules can be shared among all projects. Thus, it is better to have this centralized:
    -Removing interconnect configuration from minsoc_defines.v. There is an interconnect_defines.v file on rtl/verilog. The software counterpart is interconnect.h on sw/drivers.

    Including a jsp firmware. It is basically the uart firmware but using JSP instead. Added to all board configure scripts to be compiled on configuration.

    prj/srcs extended to include jsp and interconnec_defines.v.

    spartan3e_starter_kit_eth lost UART (does not fit) and uses JSP instead now.
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[FOLDER] minsoc/ 175  4056d 06h rfajardo View Log RSS feed
[NODE][FOLDER] branches/ 153  4587d 14h rfajardo View Log RSS feed
[NODE][FOLDER] tags/ 172  4140d 07h rfajardo View Log RSS feed
[NODE][FOLDER] trunk/ 175  4056d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] backend/ 174  4091d 10h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] bench/ 162  4534d 09h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] doc/ 101  4655d 17h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] prj/ 158  4549d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 97  4664d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] scripts/ 141  4593d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 97  4664d 16h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] src/ 158  4549d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] blackboxes/ 85  4670d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] adbg_top.prj 158  4549d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] altera_virtual_jtag.prj 96  4665d 03h javieralso View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] ethmac.prj 141  4593d 14h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] jtag_top.prj 85  4670d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_bench.prj 88  4670d 08h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] minsoc_top.prj 158  4549d 05h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] or1200_top.prj 85  4670d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][NODE][FILE] uart_top.prj 85  4670d 09h rfajardo View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 97  4664d 16h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 175  4056d 06h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sim/ 166  4440d 15h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] sw/ 158  4549d 05h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] syn/ 141  4593d 14h rfajardo View Log RSS feed
[NODE][NODE][FOLDER] utils/ 170  4208d 10h ConX. View Log RSS feed

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