URL https://opencores.org/ocsvn/minsoc/minsoc/trunk

Subversion Repositories minsoc

[/] [minsoc/] [trunk/] [rtl/] [verilog/] - Rev 173

Rev 173 2013-04-07 14:44:43 GMT
Author: rfajardo
Log message:
Jay Aurabind's contribution of a port to the Nexys 3 board from Digilent. Thanks!!

Path	Last modification			Log	RSS feed
minsoc/	173	4249d 04h	rfajardo	View Log	RSS feed
branches/	153	4745d 08h	rfajardo	View Log	RSS feed
tags/	172	4298d 01h	rfajardo	View Log	RSS feed
trunk/	173	4249d 04h	rfajardo	View Log	RSS feed
backend/	173	4249d 04h	rfajardo	View Log	RSS feed
bench/	162	4692d 04h	rfajardo	View Log	RSS feed
doc/	101	4813d 12h	rfajardo	View Log	RSS feed
prj/	158	4707d 00h	rfajardo	View Log	RSS feed
rtl/	173	4249d 04h	rfajardo	View Log	RSS feed
verilog/	173	4249d 04h	rfajardo	View Log	RSS feed
minsoc_startup/	12	5504d 00h	rfajardo	View Log	RSS feed
altera_pll.v	63	4958d 02h	rfajardo	View Log	RSS feed
interconnect_defines.v	158	4707d 00h	rfajardo	View Log	RSS feed
minsoc_clock_manager.v	62	4958d 09h	rfajardo	View Log	RSS feed
minsoc_onchip_ram.v	173	4249d 04h	rfajardo	View Log	RSS feed
minsoc_onchip_ram_top.v	7	5532d 03h	rfajardo	View Log	RSS feed
minsoc_tc_top.v	163	4686d 09h	rfajardo	View Log	RSS feed
minsoc_top.v	158	4707d 00h	rfajardo	View Log	RSS feed
minsoc_xilinx_internal_jtag.v	173	4249d 04h	rfajardo	View Log	RSS feed
timescale.v	70	4947d 09h	rfajardo	View Log	RSS feed
xilinx_dcm.v	173	4249d 04h	rfajardo	View Log	RSS feed
sim/	166	4598d 09h	rfajardo	View Log	RSS feed
sw/	158	4707d 00h	rfajardo	View Log	RSS feed
syn/	141	4751d 08h	rfajardo	View Log	RSS feed
utils/	170	4366d 04h	ConX.	View Log	RSS feed