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[/] [mod_sim_exp/] [tags/] [Release_1.5/] [rtl/] [vhdl/] - Rev 89
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Last modification
- Rev 89 2013-04-24 20:19:10 GMT
- Author: JonasDC
- Log message:
- updated vhdl files so now different clock frequencies are posible for the core and bus interface.