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https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk
Subversion Repositories mod_sim_exp
[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] - Rev 39
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Last modification
- Rev 39 2012-11-12 21:18:13 GMT
- Author: JonasDC
- Log message:
- changed files to remove warnings from synthesis
last cell logic is simplified because of redundant logic