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[/] [mod_sim_exp/] [trunk/] [rtl/] [vhdl/] [interface/] - Rev 89

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Last modification

  • Rev 89 2013-04-24 20:19:10 GMT
  • Author: JonasDC
  • Log message:
    updated vhdl files so now different clock frequencies are posible for the core and bus interface.
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 89  4211d 20h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 68  4261d 03h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 80  4247d 21h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 89  4211d 20h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 84  4219d 06h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 88  4217d 20h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 89  4211d 20h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] vhdl/ 89  4211d 20h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] core/ 89  4211d 20h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] interface/ 89  4211d 20h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] axi/ 89  4211d 20h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] plb/ 84  4219d 06h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ram/ 89  4211d 20h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 84  4219d 06h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4380d 20h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 72  4261d 00h JonasDC View Log RSS feed

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