OpenCores
URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] [trunk/] [syn/] [altera/] [log/] - Rev 71

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 71 2013-03-06 15:27:23 GMT
  • Author: JonasDC
  • Log message:
    added synthesis report for altera and xilinx for the new ram.
    added coregen sources for xilinx for primitive RAM
Path Last modification Log RSS feed
[FOLDER] mod_sim_exp/ 71  4308d 12h JonasDC View Log RSS feed
[NODE][FOLDER] branches/ 68  4308d 14h JonasDC View Log RSS feed
[NODE][FOLDER] tags/ 49  4335d 08h JonasDC View Log RSS feed
[NODE][FOLDER] trunk/ 71  4308d 12h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] bench/ 70  4308d 12h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] doc/ 47  4403d 13h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] rtl/ 69  4308d 12h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sim/ 70  4308d 12h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] sw/ 29  4428d 07h JonasDC View Log RSS feed
[NODE][NODE][FOLDER] syn/ 71  4308d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera/ 71  4308d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] log/ 71  4308d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] fifo/ 71  4308d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] mod_sim_exp_core/ 71  4308d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] operand_mem/ 71  4308d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ver011_msec_genRAM_res.htm_files/ 64  4316d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] ver011_msec_genRAM_sum.htm_files/ 64  4316d 12h JonasDC View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx/ 71  4308d 12h JonasDC View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.