OpenCores
URL https://opencores.org/ocsvn/open8_urisc/open8_urisc/trunk

Subversion Repositories open8_urisc

[/] [open8_urisc/] [trunk/] - Rev 263

Rev

Go to most recent revision | Changes | View Log | RSS feed

Last modification

  • Rev 263 2020-07-10 23:00:32 GMT
  • Author: jshamlet
  • Log message:
    Fixed a very old bug in the CPU core where autoincrements weren't affecting the upper register in the pair, causing it to loop around the lower 256 bytes. This only affected LDX/LDO, as the proper ALU signals were being generated in STO/STX and UPP. Wow, that bug has been in there for AGES.

    Also separated the SDLC TX and RX interrupts so that they could be handled separately.
Path Last modification Log RSS feed
[FOLDER] open8_urisc/ 263  1446d 05h jshamlet View Log RSS feed
[NODE][FOLDER] branches/ 4  5587d 02h root View Log RSS feed
[NODE][FOLDER] tags/ 4  5587d 02h root View Log RSS feed
[NODE][FOLDER] trunk/ 263  1446d 05h jshamlet View Log RSS feed
[NODE][NODE][FOLDER] Documents/ 241  1509d 05h jshamlet View Log RSS feed
[NODE][NODE][FOLDER] gnu/ 179  1582d 05h jshamlet View Log RSS feed
[NODE][NODE][FOLDER] Open8 Tools/ 178  1582d 05h jshamlet View Log RSS feed
[NODE][NODE][FOLDER] VHDL/ 263  1446d 05h jshamlet View Log RSS feed
[NODE][NODE][FILE] Sample Projects.zip 240  1511d 09h jshamlet View Log RSS feed
[NODE][FOLDER] web_uploads/ 6  5586d 14h root View Log RSS feed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.