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[/] [openmsp430/] [trunk/] [core/] [bench/] [verilog/] - Rev 145

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Last modification

  • Rev 145 2012-05-30 21:03:05 GMT
  • Author: olivier.girard
  • Log message:
    Add Dhrystone and CoreMark benchmarks to the simulation environment.
Path Last modification Log RSS feed
[FOLDER] openmsp430/ 145  4562d 07h olivier.girard View Log RSS feed
[NODE][FOLDER] branches/ 1  5627d 08h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5627d 08h root View Log RSS feed
[NODE][FOLDER] trunk/ 145  4562d 07h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] core/ 145  4562d 07h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] bench/ 145  4562d 07h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] verilog/ 145  4562d 07h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] dbg_uart_tasks.v 134  4631d 07h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] msp_debug.v 134  4631d 07h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] ram.v 103  5014d 13h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] registers.v 145  4562d 07h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] tb_openMSP430.v 134  4631d 07h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FILE] timescale.v 103  5014d 13h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] doc/ 2  5627d 06h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] rtl/ 134  4631d 07h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] sim/ 145  4562d 07h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] synthesis/ 139  4599d 17h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 140  4599d 08h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 143  4583d 08h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 133  4631d 07h olivier.girard View Log RSS feed

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