Subversion Repositories openmsp430

Last modification

• Rev 33 2009-12-29 18:18:00 GMT
• Author: olivier.girard

• Log message:

  In order to avoid confusion, the following changes have been implemented to the Verilog code:
  - renamed the "rom_*" ports and defines to "pmem_*" (program memory).
  - renamed the "ram_*" ports and defines to "dmem_*" (data memory).
  
  In addition, in order to prevent potential conflicts with the Verilog defines of other IPs, a Verilog undefine file has been created.