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[/] [openmsp430/] [trunk/] [fpga/] - Rev 81

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Last modification

  • Rev 81 2010-12-05 21:45:34 GMT
  • Author: olivier.girard
  • Log message:
    Initial synthesis, P&R setup for the Actel example project.
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[FOLDER] openmsp430/ 81  5104d 06h olivier.girard View Log RSS feed
[NODE][FOLDER] branches/ 1  5627d 08h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5627d 08h root View Log RSS feed
[NODE][FOLDER] trunk/ 81  5104d 06h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] core/ 80  5104d 14h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 74  5203d 08h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 81  5104d 06h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] actel_m1a3pl_dev_kit/ 81  5104d 06h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera_de1_board/ 79  5116d 08h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx_diligent_s3board/ 79  5116d 08h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 78  5118d 08h olivier.girard View Log RSS feed

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