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[/] [openmsp430/] [trunk/] [fpga/] [OBSOLETE/] [altera_de1_board/] - Rev 98

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Last modification

  • Rev 98 2011-02-28 20:20:51 GMT
  • Author: olivier.girard
  • Log message:
    Added support for VCS verilog simulator.
    VPD and TRN waveforms can now be generated.
Path Last modification Log RSS feed
[FOLDER] openmsp430/ 98  5025d 09h olivier.girard View Log RSS feed
[NODE][FOLDER] branches/ 1  5633d 09h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5633d 09h root View Log RSS feed
[NODE][FOLDER] trunk/ 98  5025d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] core/ 98  5025d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 74  5209d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 98  5025d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] actel_m1a3pl_dev_kit/ 98  5025d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera_de1_board/ 98  5025d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx_diligent_s3board/ 98  5025d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 97  5026d 08h olivier.girard View Log RSS feed

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