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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [rtl/] - Rev 84

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Last modification

  • Rev 84 2011-01-23 20:00:36 GMT
  • Author: olivier.girard
  • Log message:
    Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
    Update watchdog to fix NMI synchronisation problem.
    Add synchronizers for the PUC signal in the debug interface.
Path Last modification Log RSS feed
[FOLDER] openmsp430/ 84  5055d 01h olivier.girard View Log RSS feed
[NODE][FOLDER] branches/ 1  5627d 01h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5627d 01h root View Log RSS feed
[NODE][FOLDER] trunk/ 84  5055d 01h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] core/ 84  5055d 01h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 74  5203d 01h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 84  5055d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] actel_m1a3pl_dev_kit/ 84  5055d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] bench/ 80  5104d 08h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] doc/ 80  5104d 08h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] rtl/ 84  5055d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] verilog/ 84  5055d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim/ 82  5101d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] software/ 84  5055d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] synthesis/ 82  5101d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera_de1_board/ 84  5055d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx_diligent_s3board/ 84  5055d 01h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 78  5118d 01h olivier.girard View Log RSS feed

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