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[/] [openmsp430/] [trunk/] [fpga/] [actel_m1a3pl_dev_kit/] [synthesis/] [actel/] - Rev 111

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  • Rev 111 2011-05-20 20:39:02 GMT
  • Author: olivier.girard
  • Log message:
    Re-organized the "openMSP430_defines.v" file.
    Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
    Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
    As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
Path Last modification Log RSS feed
[FOLDER] openmsp430/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][FOLDER] branches/ 1  5631d 02h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5631d 02h root View Log RSS feed
[NODE][FOLDER] trunk/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] core/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 100  5022d 00h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] actel_m1a3pl_dev_kit/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] bench/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] doc/ 80  5108d 08h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] rtl/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] software/ 84  5059d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] synthesis/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] actel/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] design_constraints.pdc 82  5105d 02h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] design_constraints.post.sdc 82  5105d 02h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] design_constraints.pre.sdc 82  5105d 02h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] design_files.v 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] libero_designer.tcl 82  5105d 02h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] prepare_implementation.tcl 107  4997d 23h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] synplify.tcl 82  5105d 02h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera_de1_board/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx_diligent_s3board/ 111  4942d 01h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 110  4943d 01h olivier.girard View Log RSS feed

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