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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_avnet_lx9microbard/] [bench/] - Rev 167

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Last modification

  • Rev 167 2012-12-06 21:04:46 GMT
  • Author: olivier.girard
  • Log message:
    Update LX9 Microboard FPGA example.
    It now includes a dual-core oMSP system with a shared 16kB program memory.
    Each core has its own 2kB data memory and an additional 2kB shared data memory.
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[FOLDER] openmsp430/ 167  4350d 00h olivier.girard View Log RSS feed
[NODE][FOLDER] branches/ 1  5605d 01h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5605d 01h root View Log RSS feed
[NODE][FOLDER] trunk/ 167  4350d 00h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] core/ 154  4402d 00h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 166  4358d 22h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 167  4350d 00h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] actel_m1a3pl_dev_kit/ 155  4401d 23h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera_de1_board/ 155  4401d 23h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx_avnet_lx9microbard/ 167  4350d 00h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] bench/ 167  4350d 00h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] verilog/ 167  4350d 00h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] doc/ 157  4401d 23h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] rtl/ 167  4350d 00h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim/ 167  4350d 00h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] software/ 167  4350d 00h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] synthesis/ 167  4350d 00h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx_diligent_s3board/ 155  4401d 23h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 163  4390d 23h olivier.girard View Log RSS feed

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