Subversion Repositories openmsp430

Last modification

• Rev 205 2015-07-15 20:59:52 GMT
• Author: olivier.girard

• Log message:

  Thanks again to Johan W. good feedback, the following updates are implemented:
  - Change code to fix delta cycle issues on some simulators in mixed VHDL/Verilog environment.
  - Update oscillators enable generation to relax a critical timing paths in the ASIC version.
  - Add option to scan fix inverted clocks in the ASIC version (disabled by default as this is supported by most tools).