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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] - Rev 204
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Last modification
- Rev 204 2015-07-08 20:34:10 GMT
- Author: olivier.girard
- Log message:
- Fix DMA interface RTL merge problem (defines got wrong values). Fix CDC issue with the timerA (thanks to Johan for catching that).