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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [rtl/] [verilog/] - Rev 84
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Last modification
- Rev 84 2011-01-23 20:00:36 GMT
- Author: olivier.girard
- Log message:
- Update SRAM model in the core testbench to prevent the IEEE warning when running simulations.
Update watchdog to fix NMI synchronisation problem.
Add synchronizers for the PUC signal in the debug interface.