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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [sim/] [rtl_sim/] - Rev 23

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Last modification

  • Rev 23 2009-08-30 16:39:26 GMT
  • Author: olivier.girard
  • Log message:
    Renamed the "openMSP430.inc" file to "openMSP430_defines.v" & added the "timescale.v" file.
    In order to follow the same structure as other OpenCores projects, the timescale and the defines are now included from within the Verilog files (using the `include construct).
Path Last modification Log RSS feed
[FOLDER] openmsp430/ 23  5569d 21h olivier.girard View Log RSS feed
[NODE][FOLDER] branches/ 1  5630d 17h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5630d 17h root View Log RSS feed
[NODE][FOLDER] trunk/ 23  5569d 21h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] core/ 23  5569d 21h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 23  5569d 21h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 23  5569d 21h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] diligent_s3board/ 23  5569d 21h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 15  5595d 16h olivier.girard View Log RSS feed

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