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[/] [openmsp430/] [trunk/] [fpga/] [xilinx_diligent_s3board/] [synthesis/] [xilinx/] - Rev 111

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  • Rev 111 2011-05-20 20:39:02 GMT
  • Author: olivier.girard
  • Log message:
    Re-organized the "openMSP430_defines.v" file.
    Re-defined the CPU_ID register of the debug interface (in particular to support custom user versioning).
    Added RTL configuration possibility to expand the peripheral address space from 512B (0x0000 to 0x0200) to up to 32kB (0x0000 to 0x8000).
    As a consequence the per_addr bus width goes from 8 to 14 bits and the peripherals address decoders have been updated accordingly.
Path Last modification Log RSS feed
[FOLDER] openmsp430/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][FOLDER] branches/ 1  5512d 09h root View Log RSS feed
[NODE][FOLDER] tags/ 1  5512d 09h root View Log RSS feed
[NODE][FOLDER] trunk/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] core/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] doc/ 100  4903d 08h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] fpga/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] actel_m1a3pl_dev_kit/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] altera_de1_board/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][FOLDER] xilinx_diligent_s3board/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] bench/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] doc/ 2  5512d 08h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] rtl/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] sim/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] software/ 106  4879d 07h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][FOLDER] synthesis/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][FOLDER] xilinx/ 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] create_bitstream.bat 26  5340d 17h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] create_bitstream.sh 109  4877d 17h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] load_pmem.bat 37  5330d 08h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] load_pmem.sh 73  5113d 10h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] memory.bmm 2  5512d 08h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] openMSP430_fpga.prj 111  4823d 09h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] openMSP430_fpga.ucf 26  5340d 17h olivier.girard View Log RSS feed
[NODE][NODE][NODE][NODE][NODE][NODE][FILE] xst_verilog.opt 71  5262d 09h olivier.girard View Log RSS feed
[NODE][NODE][FOLDER] tools/ 110  4824d 09h olivier.girard View Log RSS feed

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