Subversion Repositories openrisc

Last modification

• Rev 787 2012-03-23 10:11:51 GMT
• Author: jeremybennett

• Log message:

  Patch from R Diez to zero R0 on startup. ChangeLog from testsuite/test-code-or1k:
  
  2012-03-23 Jeremy Bennett <jeremy.bennett@embecosm.com>
  
  Patch from R Diez <rdiezmail-openrisc@yahoo.de>
  
  * cache/cache-asm.S, cfg/cfg.S, except-test/except-test-s.S,
  * except/except.S, ext/ext.S, flag/flag.S, fp/fp.S,
  * inst-set-test/inst-set-test.S, int-test/int-test.S,
  * mc-common/except-mc.S, uos/except-or32.S: Clear R0 on
  start-up. There is no guarantee that R0 is hardwired to zero, and
  indeed it is not when simulating the or1200 Verilog core.
  * configure: Regenerated.
  * configure.ac: Updated version.