URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Last modification

• Rev 411 2010-11-04 13:09:21 GMT
• Author: julius

• Log message:

  Improved ethmac testbench and software.
  
  Renamed some OR1200 library functions to be more generic.
  
  Fixed bug with versatile_mem_ctrl for Actel board.
  
  Added ability to simulate gatelevel modules alongside RTL modules
  in board build.

Path	Last modification			Log	RSS feed
openrisc/	411	5258d 19h	julius	View Log	RSS feed
branches/	1	5820d 23h	ocadmin	View Log	RSS feed
tags/	388	5291d 17h	jeremybennett	View Log	RSS feed
trunk/	411	5258d 19h	julius	View Log	RSS feed
bootloaders/	406	5260d 11h	julius	View Log	RSS feed
docs/	359	5313d 21h	julius	View Log	RSS feed
gnu-patches/	170	5381d 19h	jeremybennett	View Log	RSS feed
gnu-src/	404	5260d 15h	jeremybennett	View Log	RSS feed
linux/	380	5293d 16h	julius	View Log	RSS feed
or1ksim/	387	5291d 17h	jeremybennett	View Log	RSS feed
or1k_startup/	2	5820d 22h	marcus.erlandsson	View Log	RSS feed
or1200/	401	5261d 18h	julius	View Log	RSS feed
orpsocv2/	411	5258d 19h	julius	View Log	RSS feed
or_debug_proxy/	376	5298d 23h	julius	View Log	RSS feed
rtos/	174	5381d 18h	jeremybennett	View Log	RSS feed
toolchain_install_scripts/	407	5260d 10h	julius	View Log	RSS feed
uClibc/	382	5293d 16h	julius	View Log	RSS feed